vht4?1/4 vk d MC74VHC1GT04 vk d 1 3 2 4 5 sot?23/tsop?5/sc?59 dt suffix case 483 the MC74VHC1GT04 is a single gate inverting buffer fabricated with silicon gate cmos technology. it achieves high speed operati on similar to equivalent bipolar schottky ttl while maintaining cmos low power dissipation. the internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable outpu t. the device input is compatible with ttl?type input thresholds and the output has a full 5 v cmos level output swing. the input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic?level translator from 3.0 v cmos logic to 5.0v cmos logic or from 1.8 v cmos logic to 3.0 v cmos logic while operating at the high?voltage power supp ly. the MC74VHC1GT04 input structure provides protection when voltages up to 7 v are applied, regardless of the supply voltage. thi s allows the MC74VHC1GT04 to be used to interface 5 v circuits to 3 v circuits. the output structures also provide protection whe n v cc = 0 v. these input and output structures help prevent device destruction caused by supply voltage ? input/output voltage mismat ch, battery backup, hot insertion, etc. sc?70/sc?88a/sot?353 df suffix case 419a 1 3 2 4 5 marking diagrams pin 1 d = date code pin 1 d = date code figure 1. pinout (top view) figure 2. logic symbol pin assignment 1nc 2 in a 3 gnd 4 out y 5v cc function table inputs ou tput ay lh hl ordering information see detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. inverting buffer / cmos logic level shifter with lsttl?compatible inputs high speed: t pd = 3.8 ns (typ) at v cc = 5 v low power dissipation: i cc = 2 ma (max) at t a = 25c ttl?compatible inputs: v il = 0.8 v; v ih = 2.0 v cmos?compatible outputs: v oh > 0.8 v cc ; v ol < 0.1 v cc @load power down protection provided on inputs and outputs balanced propagation delays pin and function compatible with other standard logic families chip complexity: fets = 105; equivalent gates = 26 pin assignment
vht4?2/4 MC74VHC1GT04 recommended operating conditions symbol parameter min max unit v cc dc supply voltage 3.0 5.5 v v in dc input voltage 0.0 5.5 v v out dc output voltage v cc = 0 0.0 5.5 v high low state 0.0 v cc t a operating temperature range ? 55 + 125 c t r ,t f input rise and fall time v cc = 3.3 0.3 v 0 100 ns/v v cc = 5.0 0.5 v 0 20 device junction temperature versus time to 0.1% bond failures junction t ime, time, temperature c hours years 80 1,032,200 117.8 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 normalized failure rate figure 3. failure rate vs. time junction temperature 1 1 10 100 1000 maximum ratings symbol parameter value unit v cc dc supply voltage ? 0.5 to + 7.0 v v in dc input voltage ? 0.5 to 7.0 v v out dc output voltage v cc =0 ? 0.5 to 7.0 v high or low state ?0.5 to v cc + 0.5 i ik input diode current ?20 ma i ok output diode current v out < gnd; v out > v cc +20 ma i out dc output current, per pin + 25 ma i cc dc supply current, v cc and gnd +50 ma p d power dissipation in still air sc?88a, tsop?5 200 mw ja thermal resistance sc?88a, tsop?5 333 c/w t l lead temperature, 1 mm from case for 10 s 260 c t j junction temperature under bias + 150 c t stg storage temperature ?65 to +150 c v esd esd withstand voltage human body model (note 2) >2000 v machine model (note 3) > 200 charged device model (note 4) n/a i latch?up latch?up performance above v cc and below gnd at 125c (note 5) 500 ma 1. maximum ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute?maximum?rated conditions is not implied. functional operation should be restricted to the recommended operating conditions. 2. tested to eia/jesd22?a114?a 3. tested to eia/jesd22?a115?a 4. tested to jesd22?c101?a 5. tested to eia/jesd78 time, years
vht4?3/4 dc electrical characteristics v cc t a = 25 c t a < 85 c ?55c < t a < 125c symbol parameter test conditions (v) min typ max min max min max unit v ih minimum high?level v input voltage 3.0 1.4 1.4 1.4 4.5 2.0 2.0 2.0 5.5 2.0 2.0 2.0 v il maximum low?level v input voltage 3.0 0.53 0.53 0.53 4.5 0.8 0.8 0.8 5.5 0.8 0.8 0.8 v oh minimum high?level v in = v ih or v il v output voltage i oh = ? 50 a 3.0 2.9 3.0 2.9 2.9 v in = v ih or v il 4.5 4.4 4.5 4.4 4.4 v in = v ih or v il i oh = ?4 ma 3.0 2.58 2.48 2.34 i oh = ?8 ma 4.5 3.94 3.80 3.66 v ol maximum low?level v in = v ih or v il v output voltage i ol = 50 a 3.0 0.0 0.1 0.1 0.1 v in = v ih or v il 4.5 0.0 0.1 0.1 0.1 v in = v ih or v il i ol = 4 ma 3.0 0.36 0.44 0.52 i ol = 8 ma 4.5 0.36 0.44 0.52 i in maximum input v in = 5.5 v or gnd 0 to5.5 0.1 1.0 1.0 a leakage current i cc maximum quiescent v in = v cc or gnd 5.5 2.0 20 40 a supply current i cct quiescent supply input: v in = 3.4 v 5.5 1.35 1.50 1.65 ma current i opd output leakage v out = 5.5 v 0.0 0.5 5.0 10 a current MC74VHC1GT04 ac electrical characteristics c load = 50 pf, input t r = t f = 3.0 ns t a = 25 c t a < 85 c ?55c vht4?4/4 MC74VHC1GT04 figure 4. switching waveforms *includes all probe and jig capacitance figure 5. test circuit device ordering information device nomenclature MC74VHC1GT04dft1 mc 74 vhc1g t04 df t1 sc?70/sc?88a/ 178 mm (7 in) sot?353 3000 unit MC74VHC1GT04dft2 mc 74 vhc1g t04 df t2 sc?70/sc?88a/ 178 mm (7 in) sot?353 3000 unit MC74VHC1GT04dft4 mc 74 vhc1g t04 df t4 sc?70/sc?88a/ 330 mm (13 in) sot?353 10,000 unit MC74VHC1GT04dtt1 mc 74 vhc1g t04 dt t1 sot?23/tsops/ 178 mm (7 in) sc?59 3000 unit MC74VHC1GT04dtt3 mc 74 vhc1g t04 dt t3 sot?23/tsops/ 330 mm (13 in) sc?59 10,000 unit device order number circuit indicator temp range identifier technology device function package suffix tape & reel suffix package type (name/sot#/ common name) tape and reel size 3.0v v oh v ol
|
